The subject application is related to subject matter disclosed in the Japanese Patent Application No. Hei11-158256 filed in Jun. 4, 1999 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
1. Field of the Invention
The present invention is related to an improved information processing system which makes it possible to protect information stored in the ROM of the system from unauthorized access by means of a debug tool.
2. Description of the Related Art
FIG. 1 is an information processing system in accordance with a prior art technique provided with a microcomputer 101 in which an on-chip debug circuit 100 is embedded. The on-chip debug circuit 100 serves to make it possible to use several emulation functions such as performing single instruction step, stop on compare, break points, tracing and so forth by connecting an external on-chip debug ICE (In-Circuit Emulator) 102. By this configuration, it is possible to analyze the execution of a target program and the behavior of the microcomputer 101 for the purpose of improving the software development environment, the debug process, repairing process and so forth.
However, the information stored in a built-in ROM 103 of the microcomputer 101 can be easily read by means of the on-chip debug ICE 102. It is therefore possible to analyze and refer to the information inside of the system of the microcomputer 101 by unauthorized persons. Because of this, it is difficult to protect the information of the system from reverse engineering/decompilation by unauthorized persons.
The present invention has been made in order to solve the shortcomings as described above. It is an important object of the present invention to provide an information processing system which makes it possible to protect information stored in the ROM of the system from unauthorized access by means of a debug tool.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved information processing system comprising: a ROM for storing an unlocking program and a user program; a CPU for executing said unlocking program and said user program stored in said ROM; an on-chip debug circuit serving to output debug information of said user program as executed by said information processing system; and a debug function disabling circuit serving to disable debug functions of said on-chip debug circuit at power up and to enable the debug functions of said on-chip debug circuit when said unlocking program has been executed.
In a preferred embodiment, further improvement resides in that said debug function disabling circuit is controlled by a register for controlling the security of the information processing system.
In a preferred embodiment, further improvement resides in that said register for controlling the security is set and reset by executing input/output instructions of said CPU.
In a preferred embodiment, further improvement resides in that, when said register for controlling the security is set, said on-chip debug circuit is maintained disabled until an enable code is loaded to the clear register.
In a preferred embodiment, further improvement resides in that said debug function disabling circuit serves to disable part of the debug function(s) and enable the remaining debug function(s) at power up.
In a preferred embodiment, further improvement resides in that said debug function disabling circuit serves to disable a debug function for accessing a memory at power up.
In a preferred embodiment, further improvement resides in that said debug function disabling circuit serves to enable a debug function for performing break points.
In a preferred embodiment, further improvement resides in that, when a predetermined registration code is compared with a password as inputted to the system and confirmed the agreement therewith by said unlocking program, said debug function disabling circuit enables the function of the on-chip debug circuit.
In accordance with a further aspect of the present invention, the improvement resides in an information processing system comprising: a ROM for storing a user program; a CPU for executing said user program stored in said ROM; an on-chip debug circuit serving to output debug information of said user program as executed by said information processing system; and a debug function disabling circuit serving to disable debug functions of said on-chip debug circuit at power up and to enable the debug functions of said on-chip debug circuit by authorization using a password.
In a preferred embodiment, further improvement resides in that the authorization using a password is performed by hardwired control.
In a preferred embodiment, further improvement resides in that the authorization using a password is performed by an unlocking program stored in said ROM.
In accordance with a further aspect of the present invention, the improvement resides in an information processing system comprising: a ROM for storing a user program; a CPU for executing said user program stored in said ROM; an on-chip debug circuit serving to encrypt and output debug information of said user program as executed by said information processing system; and a debug function disabling circuit serving to disable debug functions of said on-chip debug circuit at power up and to enable the debug functions of said on-chip debug circuit by authorization using a password.
In a preferred embodiment, further improvement resides in that said on-chip debug circuit serves to decrypt a debug control signal as given from an external on-chip debug ICE.